Integrated circuit devices such as transistors are formed over semiconductor wafers. The devices are interconnected through metal lines and vias to form functional circuits. The metal lines and vias are formed in back-end-of-line processes. To reduce the parasitic capacitance of the metal lines and vias, the metal lines and vias are formed in low-k dielectric layers, which typically have k values lower than 3.8, lower than 3.0, or lower than 2.5.
In the formation of the metal lines and vias, a low-k dielectric layer is etched to form trenches and via openings. The etching of the low-k dielectric material may involve forming a hard mask and a dielectric hard mask layer over the low-k dielectric material, and using the patterned hard mask as an etching mask to form trenches. Via openings are also formed and self-aligned to the trench. The trenches and the via openings are then filled with a metallic material, which may comprise copper. A Chemical Mechanical Polish (CMP) is then performed to remove excess portions of the metallic material over the low-k dielectric material.
In the trench-first approach in the formation of the trenches and via openings, the patterns of the trenches are first defined in a hard mask layer, which is formed over a low-k dielectric layer. Via openings are then formed in the low-k dielectric layer. The vias openings stop at an intermediate level of the low-k dielectric layer. Next, the low-k dielectric layer is etched using the patterned hard mask layer as an etching mask, so that trenches and via openings extend down simultaneously, until the via openings reach the bottom of low-k dielectric layer. At this time, the bottoms of the trenches are at an intermediate level between the top surface and the bottom surface of the low-k dielectric layer. The trenches and the via openings are then filled with a conductive material to form metal lines and vias, respectively.
In the interconnect structures formed using the trench-first approach, the vias under the large trenches are significantly wider than the vias under small trenches. This may cause the leakage or dielectric breakdown issues.